ADDER X-SC Manual de usuario descargar pdf (Pagina 64)

64 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLES

In the case of the full adder we will use the following behavioral description that matches the circuit of

Figure 2.5.

-- full adder

entity fa is

port(a,b,cin,vdd,vss : in bit;

sum,cout : out bit);

end fa;

--behavior

architecture vbe of fa is

signal xor1 : bit;

begin

xor1 <= a XOR b;

cout <= b when xor1 = ’0’ else cin;

sum <= cin XOR xor1;

end vbe;

As for the half adder we run BOOM, BOOG and LOON optimizing speed (delay).

% boom -l 3 -d 0 myfa fa

% boog fa myfa -x 0 -m 4

% loon -x 0 -m 4 myfa fa

You can check that the multiplexer of the original circuit has been changed for the oa2ao222 x2 cell during the

synthesis process. We are now ready to design the adder trees and the output adder of the multiplier. We will

show in the following section the design of the adder tree.

2.1.3 Adder Tree

As we have shown in Figure 2.3, there are many ways of implementing the adder tree used in a multiplier. We

will explain here the design of the tree using the approach of Wallace[1]. The behavioral description of it is the

following one.

entity wallace4 is

port(p01,p02,p03 : in bit;

p10,p11,p12,p13 : in bit;

p20,p21,p22,p23 : in bit;

p30,p31,p32,p33 : in bit;

vdd,vss : in bit;

p1,p2,p3a,p3b,p4a,p4b,p5a,p5b,p6a,p6b,p7b : out bit);

end wallace4;

architecture structural of wallace4 is

Component ha

port(a,b : in bit;

vdd,vss : in bit;

sum,carry : out bit);

end component;

component fa

port(a,b,cin : in bit;

vdd,vss : in bit;

sum,cout : out bit);

end component;

signal h1c,f1s,f1c,f2s,f2c : bit;

signal f3s,f3c,h2s,h2c : bit;

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ADDER X-SC Manual de usuario Pagina 64

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