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34 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLS
The last line tells us that the netlists are identical, in other words that the mux design has been correctly
routed. The design verification that includes COUGAR can be visualized as shown in Figure 1.15. COUGAR
Figure 1.15: The verification flow including COUGAR.
can also extract a SPICE netlist from the design in ap format. In this case we need to set the environment
variable MBK OUT LO to spi and MBK SPI MODEL (we only show the setting for a C shell).
% setenv MBK_OUT_LO spi
% setenv MBK_SPI_MODEL $ALLIANCE_TOP/etc/spimodel.cfg
Then, we can extract the SPICE netlist as follows.
% COUGAR -t muxoor mux_oo
@@@@ @
@@ @@
@@ @
@@ @ @@@ @@@ @@@@ @@@@@@ @@@@ @@@ @@@
@@ @@ @@ @@ @@ @@ @@ @@ @ @@@ @@
@@ @@ @@ @@ @@ @ @@ @@ @@ @@ @@
@@ @@ @@ @@ @@ @ @ @@@@@ @@
@@ @@ @@ @@ @@ @@@ @@ @@ @@
@@ @ @@ @@ @@ @@ @@ @@ @@ @@
@@ @@ @@ @@ @@ @@@ @@@@@@ @@ @@@ @@
@@@@ @@@ @@@@ @@ @@ @@@ @@@@ @@ @@@@
@ @
@@@@@
Netlist extractor ... formerly Lynx
Alliance CAD System 5.0 20040928, COUGAR 1.21
Copyright (c) 1998-2005, ASIM/LIP6/UPMC
Author(s): Ludovic Jacom me and Gregoire Avot
Contributor(s): Picault Stephane
E-mail : [email protected]
---> Extract symbolic figure muxoor
<--- done !
---> Total extracted capacitance
<--- 0.0pF
This kind of netlist can then s imulated with a SPICE simulator if we provide an adequate transistor model
card.
1.6 DREAL
This tool is a hierarchical real layout editor similar to graal (the tool we used to visualize the placed and routed
designs), but it has no design rule checker neither an extractor as graal does. We use DREAL providing the
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