ADDER X-SC Manual de usuario

Introduction to VLSI CMOS Circuits Design1Carlos Silva CardenasCatholic University of Per´uTakeo YoshidaUniversity of the RyukyusAlberto Palacios Pawl

10 LIST OF TABLES

Chapter 1Introduction to the Alliance ToolsThe set of tools provided by Alliance lets us design and test a circuit from its specification to its layout

12 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSLet’s check this circuit description with ASIMUT. But before that, let’s check that the environment va

1.1. ASIMUT 13ASIMUT will detect the error and will give the following output:% asimut -b -c mux@ @@@@ @ @ @@@@@@@@@@@ @ @@ @@@ @ @@ @@@@ @@ @ @ @ @@

14 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSEvery input pattern file has the following general format:-- description of the input and outp ut ports

1.1. ASIMUT 15Figure 1.3: The mux in.pat shown by xpat.generate the corresponding output pattern file. We run this time ASIMUT as follows.% asimut -b m

16 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSnamed mux in and that we want the output pattern file generated by the simulation to be named mux out(N

1.1. ASIMUT 17Table 1.1: Options in ASIMUT.Option Description-bThe RTL circuit description is a behavioral one-backdelay [min, max, typ] delayfile Use

18 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSTable 1.2: Set of types used in the VHDL subset of Alliance.Type DescriptionbitThe standard bit type:

1.1. ASIMUT 19Figure 1.6: One possible structural configuration of our multiplexer circuit.entity mux isport (a : in bit;b : in bit;c : in bit;q : out

2

20 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSIn this way we can build any hierarchical design. But remember that if the corresponding circuit is at

1.1. ASIMUT 21indicate that both, delay and area must be optimized. The corresponding output will be as follows.% boog invg_o invg -x 1 -m 2@@@@@@@ @@

22 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSthose of the behavioral description. This time we get the following output.% asimut mux mux_in muxst_o

1.1. ASIMUT 23flow).% env | grep MBKMBK_IN_LO=vstMBK_OUT_LO=vstMBK_IN_PH=apMBK_OUT_PH=apMBK_WORK_LIB=.MBK_CATAL_NAME=CATALMBK_SCALE_X=100MBK_CATA_LIB=.

24 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSpages), shows the use of resolved and guarded signals.begin first_driver_of_mux : block (Sel1 = ’1’) b

1.2. B2F 25will use the following VHDL description of a simple controller.library IEEE;use IEEE.std_logic_1164.all;entity RWFSM isport(CLK : in std_lo

26 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSFigure 1.8: The rwgraph.fsm shown by xfsm.1.3 BOOGThe BOOG (Binding and Optimizing On Gates) tool maps

1.4. BOOM 27its logic function. This tool gives good results for small random logic but is not usable in datapath optimization.We use this tool given

28 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSoutput file to visualize all the delay paths of it. Running BOOG will give the following output.% boog

1.5. COUGAR 29Figure 1.10: The mux.vst shown by xsch.Figure 1.11: The mux oo.vst shown by xsch.and a complex and-or gate (both have been chosen by BOO

Contents1 Introduction to the Alliance Tools 111.1 ASIMUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSTable 1.7: Options Available for the COUGAR Tool.Option Description-tNotifies a transistor level extrac

1.5. COUGAR 31can now route the placed mux design with the Alliance NERO tool as follows.% nero -V -p muxoop mux_oo muxoor@@@ @@@ @@@@@@@@@ @ @@ @@@@@

32 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSWe told NERO to run in verbose mode, to use the muxoop placement file of the mux oo netlist and generat

1.5. COUGAR 33That will return the environment variable value. Once set this variable we use COUGAR as follows.% COUGAR muxoor muxooc@@@@ @@@ @@@@ @@@

34 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSThe last line tells us that the netlists are identical, in other words that the mux design has been co

1.6. DREAL 35following command.% dreal [-l file_name] [-xor] [-debug] [-install] [-force]The options available in DREAL are shown in Table 1.8. This t

36 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSThe corresponding real layout (after flattening) is shown in Figure 1.16.Figure 1.16: The real layout o

1.8. FLATBEH 37As could be notice from the output, no errors has been detected. And the layout generated by OCP and NEROdoes not contain violations to

38 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSWe can test this circuit with ASIMUT using a modified version of mux in.pat (muxoo in.pat).-- terminals

1.9. FLATLO 39Checking in this way that the generated behavioral description is also correct.1.9 FLATLOThe FLATLO (FLATtens LOgical) tool inputs a hie

4 CONTENTS

40 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSexample used with the B2F tool.% fmi -V rwgraph rwmin@@@@@@@@@ @@@ @@@ @@@@@@@@ @ @@ @@ @@@@ @ @@@ @@@

1.12. FSP 411.12 FSPThe FSP (Finite State machine Proof) tool checks the equivalence of two FSM descriptions. It does it formallyusing a product based

42 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSTable 1.14: Options Available for the GENPAT Tool.Option Description-vVerbose mode.-kKeeps the executa

1.14. GRAAL 43We can check if the input pattern file is c orrect viewing it with xpat. You must see the output shown inFigure 1.17. There are several f

44 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSB2F tool.% k2f fsm kiss2 rwgraph@@@@ @@@@ @@@@ @@@@@@@@@@@ @ @ @@ @@ @@@ @ @@ @@ @@ @@@ @ @@@ @@ @@@@

1.16. L2P 45Table 1.16: Options Available for the L2P Tool.Option Description-colorGenerates a color PostScript file. The default value gives a black a

46 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSsymbolic routed multiplexer design.% l2p muxoor@@@@@@ @@@@ @@@@@@@@@ @ @@ @@ @@@@ @@ @@ @@ @@@@ @@@ @@

1.17. LOON 471.17 LOONLOON (Light Optimizing On Nets) is a command line tool of Alliance that is used in the synthesis process afterapplying BOOM and

48 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSOf course, in the case of this very simple design, there will be no changes in the description already

1.20. NERO 49tool in its manual pages. We have called both files fsm.vhd and fsm.ctl respectively. We first convert the VHDLfile in a behavioral descript

List of Figures1.1 A 2-input multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111.2 Checking the corre

50 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSTable 1.20: Options Available for the NERO Tool.Option Description-h, –help Prints help.-v, –verboseVe

1.22. PROOF 51will prepare the design for the ring pad placement. In this case we use the following command.% ocp -ring mux_ool muxoolpring@@@ @@@@ @

52 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSTable 1.22: Options Available for the proof Tool.Option Description-aThis option asks proof to keep th

1.23. RING 53of two behavioral descriptions.1.23 RingRing is the pad ring router of Alliance. It is used with the following command (it has no options

54 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSThe inserted scan path will contain all the registers specified in the file specified by the pathfile (.pa

1.27. VASY 55Alliance. We run SYF on the mips seq.fsm file already created in that tutorial. We will run SYF as follows.% syf -o -V mips_seq mips_seqs@

56 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLSTable 1.26: Options Available for the VASY Tool.Option Description-DSets Debug mode on. As option [Lev

1.31. XSCH 57Table 1.28: Options Available for the XPAT Tool.Option Description-l filenameLoad the filename (with or without extension)-xorTwo graphic c

58 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLS

Chapter 2Combinational Design ExamplesIn chapter 1 we have briefly seen how to use most of the tools in Alliance. In this chapter we will explainthe de

6 LIST OF FIGURES

60 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLES(a) (b) (c)Figure 2.3: Three adder-tree schemes. (a) Wallace’s (b) Dadda’s (c) Palacios’sFigure 2.4: Half a

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 61Figure 2.7: Design hierarchy of the multiplier.2.1.1 Design of the partial product generator

62 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESIf you check the output file obtained with BOOM you will notice that it does not improve the already givende

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 63With this we have a synthesized structural description of our original partial product gener

64 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESIn the case of the full adder we will use the following behavioral description that matches the circuit ofF

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 65begin-- Wallace tree-- first levelha1 : haport map(a => p01, b => p10,vdd => vdd, v

66 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESThis completes the synthesis pro ce ss for the adder tree. In the following section we design the last bloc

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 672.1.5 4-bit MultiplierSince we have all the components of our multiplier we can start with a

68 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESAs we have already donw before, we use first FlatBeh to obtain a behavioral representation of our multiplier

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 69Then we use BOOG to map the description on the cell library provided by Alliance.% boog mult

List of Tables1.1 Options in ASIMUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171.2 Set of types used in

70 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESFinally with LOON we reduce delays (which will insert buffers where appropiate).% loon -x 0 -m 4 smultiplier

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 71We are now ready to take our design into the layout phase in the design process. We use first

72 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESbe noticed from this figure we could extract with Cougar a structural description from the routed design file

2.1. THE DESIGN OF A 4-BIT MULTIPLIER USING ADDER TREES 73We are now ready to convert our symbolic design to a real one (using the technology provided

74 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESimplemented using the leaf designs we provide with the sources of the book.2.2 The use of Makefiles to autom

2.2. THE USE OF MAKEFILES TO AUTOMATE THE DESIGN FLOW 75We don’t change MBK WORK LIB since it is the same used in deriving the behavioral description.

76 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESrelation.ALLIANCE_BIN=$(ALLIANCE_TOP)/binVASY = $(ALLIANCE_BIN)/vasyASIMUT = $(ALLIANCE_BIN)/asimutBOOM = $

2.2. THE USE OF MAKEFILES TO AUTOMATE THE DESIGN FLOW 77This will generate an empty file with the name boom.done that will signal that BOOM has been ru

78 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESneed to modify it. We add to our Makefile the following lines.LOON = $(ALLIANCE_BIN)/loonloon.done : multi4.

2.2. THE USE OF MAKEFILES TO AUTOMATE THE DESIGN FLOW 79changed).% setenv MBK_CATAL_LIB $TARGET_LIBAnd, run ASIMUT using the following make command (t

8 LIST OF TABLES

80 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESWe place the design using the following command (the output has been shorthened to make it fit).% make multi

2.2. THE USE OF MAKEFILES TO AUTOMATE THE DESIGN FLOW 81We now route the design using NERO. For this, we modify our Makefile adding the following lines

82 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESone.% setenv RDS_TECHNO ../etc/techno-035.rds% setenv RDS_TECHNO_NAME $RDS_TECHNO% setenv MBK_IN_LO al% set

2.2. THE USE OF MAKEFILES TO AUTOMATE THE DESIGN FLOW 83And set a few new ones.% setenv SPI_MODEL $ALLIANCE_TOP/etc/spimodel.cfg% setenv MBK_SPI_MODEL

84 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESWe now use LVX to compare the structural description of our design with the first one extracted by Cougar.We

2.2. THE USE OF MAKEFILES TO AUTOMATE THE DESIGN FLOW 85Makefile.DRUC = $(ALLIANCE_BIN)/drucRDS_TECHNO_SYMB = ../etc/techno-symb.rdsdruc.done : lvx.don

86 CHAPTER 2. COMBINATIONAL DESIGN EXAMPLESNow we can run S2R as follows (the output has been shorthened to make it fit).% make multi4.cif/usr/local/al

Bibliography[1] C. S. Wallace, ”A suggestion for a fast multiplier,” IEEE Trans. Electron. Comput., Vol. EC-13, No.1, pp.14-17, Feb., 1964.[2] L. Dadd

PrefaceTechnology has advanced up to a point where almost anyone with the right tools and knowledge could do whatfew years ago was the task of a group